Edge
CFG edge. Corresponds to a (primitive) program statement between program points (and their states).
type asm_out = (string option * string * CilType.Lval.t) list
val hash_asm_out : asm_out -> int
val asm_out_to_yojson : asm_out -> Yojson.Safe.t
type asm_in = (string option * string * CilType.Exp.t) list
val hash_asm_in : asm_in -> int
val asm_in_to_yojson : asm_in -> Yojson.Safe.t
val _ : asm_in -> Yojson.Safe.t
type t =
| Assign of CilType.Lval.t * CilType.Exp.t
Assignments lval = exp
*)| Proc of CilType.Lval.t option * CilType.Exp.t * CilType.Exp.t list
Function calls of the form lva = fexp (e1, e2, ...)
*)| Entry of CilType.Fundec.t
Entry edge that relates function declaration to function body. You can use * this to initialize the local variables.
*)| Ret of CilType.Exp.t option * CilType.Fundec.t
Return edge is between the return statement, which may optionally contain * a return value, and the function. The result of the call is then * transferred to the function node!
*)| Test of CilType.Exp.t * bool
The true-branch or false-branch of a conditional exp
*)| ASM of string list * asm_out * asm_in
Inline assembly statements, and the annotations for output and input * variables.
*)| VDecl of CilType.Varinfo.t
VDecl edge for the variable in varinfo. Whether such an edge is there for all * local variables or only when it is not possible to pull the declaration up, is * determined by alwaysGenerateVarDecl in cabs2cil.ml in CIL. One case in which a VDecl * is always there is for VLA. If there is a VDecl edge, it is where the declaration originally * appeared
*)| Skip
This is here for historical reasons. I never use Skip edges!
*)val hash : t -> int
val pretty : unit -> t -> GoblintCil.Pretty.doc
val pretty_plain : unit -> t -> GoblintCil.Pretty.doc
val to_yojson : t -> [> `Assoc of (string * Yojson.Safe.t) list ]